Lead Perf Architect

• Seasoned Technical Leader: Experienced in architectural exploration, performance engineering, and innovation in cutting-edge systems at Meta, d-Matrix, Microsoft, and Cadence Design Systems, with a proven track record of building world-class products and leading high-perf teams.

• Expert in AI Systems: Specializes in CPU architectures, ML accelerators for hyperscalers, uncore performance modeling, and workload profiling for training and inference. Skilled in performance analysis and system optimization to drive high-performance AI solutions at Meta and Microsoft.

• Advanced Processor Architecture and Design: Led architectural exploration and performance modeling for Cadence Design Systems' Tensilica DNA processor family, optimizing on-device AI performance, and investigated the impact of various techniques on power, perf, and area.

Lead Software Architect

• Chief AI Software Architect: Leads the development of software stacks for next-generation AI accelerators, focusing on optimizing AI workloads and improving system performance.

• Previous Experience: Worked on enabling machine learning and media systems on cutting-edge compute architectures, contributing to advancements in AI and visual computing.

• Academic Background: Holds a Doctorate in Computer Science from Purdue University and a Bachelor's degree from Birla Institute of Technology and Science, Pilani, with a strong focus on machine learning and compute accelerators.

Lead Microarchitect

• Expert in FPGA and Reconfigurable Computing: Led FPGA design and RTL implementation for Intel Corporation, focusing on microarchitecture and high-performance reconfigurable computing for scientific applications, including memory optimizations and custom hardware accelerators.

• CPU/SoC Microarchitecture and Design: As a CPU Microarchitect at Samsung Semiconductor, specialized in high-performance out-of-order CPU research and design methodology. At Intel, led the development of RISC-V-based processors, including embedded microprocessors and custom interconnect protocols like Avalon and AXI.

• Academic and Research Contributions: Earned a Ph.D. from the University of South Carolina, with research on floating-point accumulation on FPGAs. Published work on hardware design and optimization for large-scale scientific applications, with contributions to both FPGA and GPU-based solutions.

Lead Designer

• AI Hardware and Accelerator Design: Worked on AI accelerator chip design, specializing in numerics, memory architecture, and system-level optimizations for high-performance AI workloads.

• ASIC/SoC Design Expertise: Extensive experience in ASIC and SoC design, focusing on application-specific integrated circuits (ASICs) and custom hardware solutions for AI and machine learning.

• Leadership in Major Tech Companies: Held leadership roles at top companies such as Meta, Luminous Computing, and Groq, contributing to the design and development of cutting-edge AI accelerators and logic design for advanced AI chips.

• Independent Consulting in Hardware Design: Offered independent consulting services specializing in ASIC/SoC design, providing expertise across multiple hardware design projects for various industries, with prior roles at Broadcom, Lucent Technologies, and NetLogic Microsystems.