Meet the SiliGenius

Your AI powered Genius Guide to Chip Innovation

Computer Architecture

Basic Concepts

  1. What is Computer Architecture?
    The design and organization of a computer system’s hardware and interaction with software.

  2. What are the primary components of a CPU?
    Arithmetic Logic Unit (ALU), Control Unit (CU), and Registers.

  3. What is an Instruction Set Architecture (ISA)?
    A set of machine-level instructions supported by a processor.

  4. Differentiate between RISC and CISC architectures.
    RISC (Reduced Instruction Set Computing) uses simpler, fixed-size instructions, while CISC (Complex Instruction Set Computing) supports complex, variable-length instructions.

  5. What is pipelining in CPUs?
    A technique where multiple instruction stages are processed in parallel to increase throughput.

  6. What are pipeline hazards?
    Situations that stall the pipeline: Structural, Data, and Control hazards.

  7. What is out-of-order execution?
    A method where instructions are executed based on resource availability rather than program order.

  8. What is speculative execution?
    Executing instructions before certainty to optimize CPU performance.

  9. What is a superscalar processor?
    A processor that issues multiple instructions per cycle by using multiple execution units.

  10. What is branch prediction?
    A mechanism to guess branch outcomes to reduce pipeline stalls.

Advanced CPU Design

  1. What is Tomasulo’s algorithm?
    A technique for dynamic scheduling and out-of-order execution.

  2. Define register renaming.
    A method to avoid false dependencies by assigning unique registers to variables.

  3. What is hyperthreading?
    A technique that enables a single CPU core to execute multiple threads simultaneously.

  4. What is the role of a reorder buffer (ROB)?
    To maintain instruction dependencies and ensure in-order commitment.

  5. What is VLIW (Very Long Instruction Word)?
    An architecture that executes multiple operations in a single instruction cycle.

  6. What is SIMD?
    Single Instruction, Multiple Data – a parallel computing model.

  7. What is the function of an MMU (Memory Management Unit)?
    Manages virtual-to-physical address translation.

  8. Compare Harvard vs. Von Neumann architectures.
    Harvard has separate instruction and data memory, while Von Neumann shares a single memory.

  9. What is a micro-operation (µOP)?
    A low-level instruction that breaks down a complex CPU instruction.

  10. What is a CDB (Common Data Bus)?
    A mechanism for communication between functional units in dynamic scheduling.

Multiprocessing & Parallelism

  1. Define interconnects in multiprocessor systems.
    A communication structure for data transfer between processors.

  2. What is cache coherence?
    Ensuring data consistency in shared memory caches.

  3. What is the MESI protocol?
    A cache coherence protocol with Modified, Exclusive, Shared, and Invalid states.

  4. Explain Amdahl’s Law.
    It determines the theoretical speedup from parallel execution.

  5. What is Flynn’s Taxonomy?
    A classification of architectures: SISD, SIMD, MISD, MIMD.

  6. What is a memory barrier?
    A synchronization instruction that ensures correct memory operation order.

  7. What is NUMA?
    Non-Uniform Memory Access, where different processors experience different memory latencies.

  8. What is cache thrashing?
    Excessive cache evictions due to poor memory access patterns.

  9. What is prefetching in memory?
    Fetching data before it's needed to reduce latency.

  10. What is a directory-based cache coherence protocol?
    A centralized method for tracking shared cache blocks.

Sample FAQs

Generated from our In-house AI SiliGenius :)

Memory Subsystems

Memory Hierarchy

  1. What are the levels of memory hierarchy?
    Registers → Cache → RAM → SSD/HDD → Tape Storage.

  2. What is the difference between DRAM and SRAM?
    SRAM is faster but expensive; DRAM is slower but cheaper and requires refresh.

  3. What is virtual memory?
    An abstraction allowing processes to use more memory than physically available.

  4. What is a page fault?
    A miss in virtual memory requiring data fetch from disk.

  5. What is memory-mapped I/O?
    A technique where device registers are mapped to memory addresses.

  6. What is TLB (Translation Lookaside Buffer)?
    A cache for speeding up virtual-to-physical address translation.

  7. What is the purpose of a page table?
    To store mappings between virtual and physical memory addresses.

  8. What is demand paging?
    A technique where pages are loaded into memory only when needed.

  9. What is the working set model?
    A concept defining the number of active pages a process needs.

  10. What is NUMA-aware memory allocation?
    Optimizing memory placement in NUMA architectures for performance.

Cache & Memory Optimizations

  1. What is a direct-mapped cache?
    A cache where each block maps to exactly one location.

  2. What is a fully associative cache?
    A cache where a block can be placed anywhere.

  3. What is set-associative cache?
    A hybrid between direct-mapped and fully associative caches.

  4. What is write-back caching?
    Data is written to memory only when replaced.

  5. What is cache blocking?
    Optimizing memory accesses to improve cache performance.

  6. What is write-allocate vs. write-no-allocate?
    Determines whether writes allocate a cache line.

  7. What is a memory bank?
    A subdivision of RAM enabling parallel access.

  8. What is ECC (Error Correction Code) memory?
    A type of memory that detects and corrects errors.

  9. What is a memory fence?
    An instruction ensuring correct memory access order in multi-threading.

  10. What is memory aliasing?
    When different memory addresses refer to the same physical location.

Network-on-Chip

Interconnect Basics

  1. What is Network-on-Chip (NoC)?
    A communication network inside multi-core processors.

  2. Why is NoC better than traditional bus interconnects?
    Scalability and lower latency.

  3. What are common NoC topologies?
    Mesh, Torus, Tree, Crossbar, Butterfly, Fat-tree.

  4. What is wormhole routing?
    A packet-switching technique reducing buffer needs.

  5. What is deadlock in NoC?
    Circular packet dependencies preventing progress.

  6. What is livelock?
    Packets continuously move without reaching the destination.

  7. What is adaptive routing?
    A routing algorithm that considers network congestion.

  8. What is flit?
    A flow control unit in NoC packet-based communication.

  9. What is a crossbar switch?
    A switch fabric enabling multiple simultaneous connections.

  10. What is link contention?
    When multiple packets compete for the same NoC link.

Heterogeneous NoC

  1. What is a heterogeneous NoC?
    An NoC that connects different types of processing elements, such as CPUs, GPUs, and FPGAs.

  2. Why are heterogeneous NoCs important for modern computing?
    They enable efficient workload distribution by leveraging specialized accelerators for different tasks.

Advanced Network-on-Chip

Congestion Control in NoC

  1. What is congestion in NoC?
    A state where excessive packet traffic causes performance degradation.

  2. What are the primary causes of NoC congestion?
    High network load, inefficient routing, and limited buffer capacity.

  3. What are the different congestion control techniques in NoC?
    Packet throttling, adaptive routing, flow control mechanisms.

  4. How does adaptive routing help in congestion control?
    It dynamically selects paths based on network load to avoid congestion hotspots.

  5. What is backpressure in NoC?
    A flow control mechanism where a blocked router signals upstream routers to slow down.

  6. What is explicit congestion notification (ECN) in NoC?
    A technique where routers mark packets experiencing congestion to inform sources.

  7. What is credit-based flow control?
    A method where routers track available buffer space before forwarding packets.

  8. How does buffer occupancy impact congestion?
    High buffer occupancy leads to increased queuing delays and network bottlenecks.

  9. What is virtual channel flow control?
    Using multiple virtual channels to reduce contention and improve bandwidth.

  10. How do congestion-aware routing algorithms differ from traditional routing?
    They monitor network traffic and dynamically adjust packet paths to avoid bottlenecks.

Arbitration Mechanisms in NoC

  1. What is arbitration in NoC?
    The process of deciding which packet gets access to a shared resource.

  2. What are common arbitration policies in NoC?
    Round-robin, priority-based, fair-share, and least-recently-used (LRU).

  3. How does round-robin arbitration work in NoC?
    Each input port gets equal access in a cyclic order.

  4. What is priority-based arbitration?
    Certain packets have higher priority over others, ensuring quality of service (QoS).

  5. What is the difference between local and global arbitration?
    Local arbitration is per-router, while global arbitration considers network-wide fairness.

  6. What is lottery scheduling in NoC arbitration?
    A probabilistic arbitration technique where access is granted based on assigned tickets.

  7. What is starvation in NoC arbitration?
    When certain packets are continuously denied access due to unfair policies.

  8. How can dynamic arbitration improve NoC performance?
    It adjusts priority based on network conditions rather than static rules.

  9. What is token-based arbitration?
    A token circulates, and only the holder can access the resource.

  10. How does time-division multiplexing (TDM) arbitration work in NoC?
    Each source is assigned specific time slots to send packets.

Fault Tolerance in NoC

  1. What are common sources of faults in NoC?
    Manufacturing defects, aging, transient faults, and thermal stress.

  2. What is fault-tolerant routing?
    A technique that bypasses faulty links or routers to maintain connectivity.

  3. How does redundancy improve NoC fault tolerance?
    By providing backup paths and resources in case of failures.

  4. What is error correction in NoC?
    Using error-detecting/correcting codes (ECC) to ensure data integrity.

  5. How do NoC systems detect faults dynamically?
    Through monitoring mechanisms like heartbeat signals, parity checks, and self-tests.

Bufferless Routing in NoC

  1. What is bufferless routing?
    A NoC design where packets are deflected instead of being stored in buffers.

  2. How does deflection routing work?
    Packets that cannot be buffered are sent to alternative paths to prevent deadlocks.

  3. What are the benefits of bufferless routing?
    Reduces area, power consumption, and design complexity.

  4. What are the drawbacks of bufferless routing?
    Increased packet latency due to deflections and potential livelocks.

Topology Comparisons in NoC

  1. How does a mesh NoC topology work?
    Routers are arranged in a grid with connections to adjacent nodes.

  2. What are the advantages of a torus topology over a mesh topology?
    Wrap-around links reduce average hop distance, improving performance.

  3. How does a crossbar-based NoC differ from a bus-based NoC?
    A crossbar allows multiple simultaneous communications, while a bus is a shared medium.

  4. What is the primary advantage of a tree-based NoC topology?
    Hierarchical structure allows efficient aggregation of data and reduced contention.

Security Aspects in NoC

  1. What are the primary security threats in NoC?
    Side-channel attacks, eavesdropping, data injection, and denial-of-service (DoS).

  2. How can encryption be used to secure NoC communication?
    Encrypting packets ensures confidentiality and prevents unauthorized access.

  3. What is a hardware Trojan in NoC?
    A malicious hardware modification that can disrupt communication or leak data..