Performance Tools

Pipelined CPU Simulator

This is a 5-stage single issue CPU simulator without caches and branch prediction. However, this can be easily extended to any functionality you want such as multi-issue, multi-cycle stages, branch prediction, caches and memory.

CpuSim

Output

Multi Level Cache Simulator

This is a fixed memory latency L1, L2 cache simulator. This can be easily hooked to CPU pipeline and prefetches can be added.

CacheSim

Output

Grid NoC Simulator

Simple NoC simulator with fixed hops. Leaky bucket, topologies and other extension easily possible

NocSim

Output

Memory Subsystem Simulator

Can be extended to HBM, detailed memory controller and more complex QoS related features.

MemSim

Output

SOL: ML Accelerator + Transformer Workload

MlSim

Output

Multi-Core Simulator (SimPy)

mGridSim.py

Output